1. Field of the Invention
This invention relates to a semiconductor memory device with electrically rewritable and non-volatile memory cells, especially to an EEPROM with NAND cell units formed on an SOI substrate.
2. Description of Related Art
A NAND-type flash memory is known as one of EEPROMs (electrically erasable and programmable ROMs). A NAND-type flash memory is formed of NAND cell units, each of which has a plurality of electrically rewritable and non-volatile memory cells connected in series so that unit cell area thereof is smaller than NOR-type one, and it is easy to achieve a large capacitance. Further, data read and write being performed page by page, a high-speed performance will be achieved.
To miniaturize the NAND-type flash memory further, it will be required to miniaturize the device isolation area. However, the miniaturization of the device isolation area reads to reduction of the breakdown voltage between cells. To achieve the cell's miniaturization without the above-described breakdown voltage reduction, it is effective that the memory cell array with NAND cell units is formed on an SOI (Silicon On Insulator) substrate (for example, see Unexamined Japanese Patent Application Publication No. 2000-174241).
In a NAND-type flash memory formed of an SOI substrate, there is a fear of that carriers remained in the NAND cell channel after data write or read operation read to deterioration of the data reliability. The reason will be explained in detail below. NAND cell channel bodies are formed on an SOI substrate not only to be separated independently of each other but also to have an extremely small capacitance each, as different from a bulk-type flash memory with a memory cell array formed on a common p-type well. Further, there is usually prepared select gate transistors disposed at the both ends of the NAND cell unit.
In case the select gate transistors become off before resetting the word line drive voltages after data write or read, the channel of the NAND cell unit (i.e., NAND cell channel) is not reset, so that a carrier remained state will be generated. This is such a state that electron injection into an erased cell's floating gate (i.e., electrons thereof have been discharged) easily occurs, and becomes a cause for erratic data write and the like.